1. Field of the Invention
The present invention relates to a timing comparator, a data sampling apparatus and a testing apparatus. More particularly, the present invention relates to a timing comparator with high precision in measurement, a data sampling apparatus including the timing comparator and a testing apparatus including the timing comparator for testing a device under test.
2. Description of the Related Art
Recently, in designing a large-scale logic circuit, it is often designed with CMOS circuits and used as a product, and also in a semiconductor testing apparatus, the CMOS circuits are used in almost logic circuits. However, in the part of a timing comparator, which compares a data signal outputted from a device under test with a strobe signal, requiring high precision with regard to the semiconductor testing apparatus, a desirable precision cannot be obtained by a general macro provided by an LSI vendor or other thing resulting from tuning the macro, so the design is performed with a bipolar circuit, or a large-scale macro is prepared with a CMOS circuit.
Meanwhile, a conventional variable delay circuit is configured with a rough delay circuit whose resolution is low and variable amount is large and a fine delay circuit whose resolution is high and variable amount is the same as the rough delay circuit. The rough delay circuit which takes the propagation delay time of a delay element as its resolution, and the fine delay circuit changes the delay amount by varying the load capacity of the delay element using a variable capacity element. And in order to prevent the delay precision from deteriorating due to the change of the propagation delay time caused by the noise or the change of the environmental conditions, it is proposed to configure the rough delay circuit with a DLL circuit as disclosed, for example, in the Pamphlet of International Patent Publication No. 03/036769.
However, if the timing comparator requiring high precision is designed with the bipolar circuit or the large-scale macro is prepared with the CMOS circuit, the cost becomes high. Further, in the variable delay circuit using the conventional DLL circuit, the fine delay circuit is provided out of the feed-back system of the DLL, so the delay precision deteriorates as it is impossible to comply with the effect of the noise of the DLL circuit or the change of its environment such as the voltage or temperature.